Commit 7850f243 authored by MorgothCreator's avatar MorgothCreator

Now the driver for WS2812 is functional.

Currently will send commands to 150 LED's every one second to change the color.
parent 5bb5a06f
......@@ -5,26 +5,19 @@
* Author: MorgothCreator ( morgoth.creator@gmail.com )
*/
/*** Registers description ***/
;XL:XH = RGB_BUFF pointer
;R2:R3 = RGB_BUFF top
;R4 = byte cnt mask
;R17 = RGB_tmp
;R18 = Period to load to TCNT
;r20 = L_Value
;r21 = H_Value
.set TIMER_PERIOD = 0x14
#include "definitions.inc"
#include "delay.asm"
#include "io.asm"
/**********************************************************/
.dseg
RGB_BUFF:
.byte (130 * 3)
/**********************************************************/
.cseg
.org 0
/**********************************************************/
jmp start ; 0x68 <__ctors_end>
#ifdef _M328PDEF_INC_
jmp bad_interrupt ; /* External Interrupt Request 0 */
jmp bad_interrupt ; /* External Interrupt Request 1 */
jmp bad_interrupt ; /* Pin Change Interrupt Request 0 */
......@@ -50,76 +43,287 @@ RGB_BUFF:
jmp bad_interrupt ; /* Analog Comparator */
jmp bad_interrupt ; /* Two-wire Serial Interface */
jmp bad_interrupt ; /* Store Program Memory Read */
#else /* _ATXMEGA32E5DEF_INC_ */
jmp bad_interrupt ; /* Oscillator Failure Interrupt (NMI) */
jmp bad_interrupt ; /* External Interrupt */
jmp bad_interrupt ; /* EDMA Channel 0 Interrupt */
jmp bad_interrupt ; /* EDMA Channel 1 Interrupt */
jmp bad_interrupt ; /* EDMA Channel 2 Interrupt */
jmp bad_interrupt ; /* EDMA Channel 3 Interrupt */
jmp bad_interrupt ; /* Overflow Interrupt */
jmp bad_interrupt ; /* Compare Interrupt */
jmp bad_interrupt ; /* External Interrupt */
jmp bad_interrupt ; /* TWI Slave Interrupt */
jmp bad_interrupt ; /* TWI Master Interrupt */
jmp bad_interrupt ; /* Overflow Interrupt */
jmp bad_interrupt ; /* Error Interrupt */
jmp bad_interrupt ; /* Channel A Compare or Capture Interrupt */
jmp bad_interrupt ; /* Channel B Compare or Capture Interrupt */
jmp bad_interrupt ; /* Channel C Compare or Capture Interrupt */
jmp bad_interrupt ; /* Channel D Compare or Capture Interrupt */
jmp bad_interrupt ; /* Overflow Interrupt */
jmp bad_interrupt ; /* Error Interrupt */
jmp bad_interrupt ; /* Channel A Compare or Capture Interrupt */
jmp bad_interrupt ; /* Channel B Compare or Capture Interrupt */
jmp bad_interrupt ; /* SPI Interrupt */
jmp bad_interrupt ; /* Reception Complete Interrupt */
jmp bad_interrupt ; /* Data Register Empty Interrupt */
jmp bad_interrupt ; /* Transmission Complete Interrupt */
jmp bad_interrupt ; /* EE Interrupt */
jmp bad_interrupt ; /* SPM Interrupt */
jmp bad_interrupt ; /* Timer/Counter Underflow Interrupt */
jmp bad_interrupt ; /* Timer/Counter Compare or Capture Interrupt */
jmp bad_interrupt ; /* External Interrupt */
jmp bad_interrupt ; /* AC0 Interrupt */
jmp bad_interrupt ; /* AC1 Interrupt */
jmp bad_interrupt ; /* ACW Window Mode Interrupt */
jmp bad_interrupt ; /* ADC Channel Interrupt */
jmp bad_interrupt ; /* External Interrupt */
jmp bad_interrupt ; /* Overflow Interrupt */
jmp bad_interrupt ; /* Error Interrupt */
jmp bad_interrupt ; /* Channel A Compare or Capture Interrupt */
jmp bad_interrupt ; /* Channel B Compare or Capture Interrupt */
jmp bad_interrupt ; /* Reception Complete Interrupt */
jmp bad_interrupt ; /* Data Register Empty Interrupt */
jmp bad_interrupt ; /* Transmission Complete Interrupt */
#endif
bad_interrupt:
jmp 0
/**********************************************************/
start:
;ldi r16, (0 << TOIE0)
;sts TIMSK0, r16
/* Set the period for Timer 0 */
ldi r18, 0xFF - TIMER_PERIOD
/* Set the period for Low level */
ldi r20, 0xFF - (TIMER_PERIOD / 3)
/* Set the period for High level */
ldi r21, 0xFF - ((TIMER_PERIOD / 3) * 2)
/* Load RGB_BUFF top address for compare */
ldi r16, HIGH(RGB_BUFF + (130 * 3))
ldi r16, OSC_RC32MCREF_gm
sts OSC_DFLLCTRL, r16
ldi r16, DFLL_ENABLE_bm
sts DFLLRC32M_CTRL, r16
lds r16, OSC_CTRL
ori r16, OSC_RC32MEN_bm
sts OSC_CTRL, r16
loop_init_osc:
lds r16, OSC_STATUS
andi r16, OSC_RC32MRDY_bm
breq loop_init_osc
ldi r16, CLK_SCLKSEL_RC32M_gc
ldi r17, CCP_IOREG_gc
sts CPU_CCP, r17
sts CLK_CTRL, r16
/* Load 8 value to r0 the number of bits in a byte mask. */
//clr r16
ldi r16, 0x80
mov r0, r16
ldi r16, HIGH(RGB_BUFF + (150 * 3))
mov R3, R16
ldi r16, LOW(RGB_BUFF + (130 * 3))
ldi r16, LOW(RGB_BUFF + (150 * 3))
mov R2, R16
/* Edit the direction of pin 5 on port D ( need to be output ) */
in r16, DDRD
ori r16, (1 << 5)
out DDRD, r16
PORT_OUT
/* Edit the output level of pin 5 on port D ( need to be 0 to reset the strip ) */
in r16, PORTD
andi r16, ~(1 << 5)
out PORTD, r16
OUT_CLR
/**********************************************************/
loop_main:
wdr
rjmp loop_main
ldi r16, R_PWR
rcall set_R_buff
ldi r16, 0x00
rcall set_G_buff
ldi r16, 0x00
rcall set_B_buff
rcall send_buff
delay(1000)
ldi r16, 0x00
rcall set_R_buff
ldi r16, G_PWR
rcall set_G_buff
ldi r16, 0x00
rcall set_B_buff
rcall send_buff
delay(1000)
ldi r16, 0x00
rcall set_R_buff
ldi r16, 0x00
rcall set_G_buff
ldi r16, B_PWR
rcall set_B_buff
rcall send_buff
delay(1000)
// Pink
ldi r16, R_PWR
rcall set_R_buff
ldi r16, 0
rcall set_G_buff
ldi r16, 40
rcall set_B_buff
rcall send_buff
delay(1000)
ldi r16, 0x00
rcall set_R_buff
ldi r16, G_PWR
rcall set_G_buff
ldi r16, B_PWR
rcall set_B_buff
rcall send_buff
delay(1000)
ldi r16, R_PWR
rcall set_R_buff
ldi r16, G_PWR
rcall set_G_buff
ldi r16, 0x00
rcall set_B_buff
rcall send_buff
delay(1000)
wdr
rjmp loop_main
/**********************************************************/
slide_r_to_l:
ldi r17, R_PWR
ldi r18, 0
ldi r19, 40
ret
/**********************************************************/
set_color:
push r24
push r25
push xl
push xh
push yl
push yh
ldi xh, HIGH(RGB_BUFF)
ldi xl, Low(RGB_BUFF)
movw r24, yl
add yl, r24
adc yh, r25
add yl, r24
adc yh, r25
add xl, yl
adc xh, yh
st x++, r18
st x++, r17
st x++, r19
pop yh
pop yl
pop xh
pop xl
pop r25
pop r24
ret
/**********************************************************/
set_R_buff:
/* Load RGB_BUFF pointer */
ldi xh, HIGH(RGB_BUFF)
ldi xl, Low(RGB_BUFF)
adiw x, 1
next_byte_to_set_R:
st X, r16
adiw x, 3
cp xl, r2
cpc xh, r3
brlo next_byte_to_set_R
ret
set_G_buff:
/* Load RGB_BUFF pointer */
ldi xh, HIGH(RGB_BUFF)
ldi xl, Low(RGB_BUFF)
next_byte_to_set_G:
st X, r16
adiw x, 3
cp xl, r2
cpc xh, r3
brlo next_byte_to_set_G
ret
set_B_buff:
/* Load RGB_BUFF pointer */
ldi xh, HIGH(RGB_BUFF)
ldi xl, Low(RGB_BUFF)
adiw x, 2
next_byte_to_set_B:
st X, r16
adiw x, 3
cp xl, r2
cpc xh, r3
brlo next_byte_to_set_B
ret
clear_buff:
/* Load RGB_BUFF pointer */
ldi xh, HIGH(RGB_BUFF)
ldi xl, Low(RGB_BUFF)
clr r16
next_byte_clear_buff:
st X++, r16
cp xl, r2
cpc xh, r3
brlo next_byte_clear_buff
ret
/**********************************************************/
/*** Registers description ***/
;XL:XH = RGB_BUFF pointer
;Yl:Yh = Delay counter
;R2:R3 = RGB_BUFF top
;R4 = byte cnt mask
;R17 = RGB_tmp
send_buff:
out TCNT0, r18
/* Load RGB_BUFF pointer */
ldi xh, HIGH(RGB_BUFF)
ldi xl, Low(RGB_BUFF)
/* Connect OC0B pin */
ldi r16, (0 << COM0B1) | (1 << COM0B0) | (1 << WGM01) | (1 << WGM00)
out TCCR0A, r16
/* Activate the timmer clock */
ldi r16, (1 << WGM02) | (0 << CS02) | (0 << CS01) | (1 << CS00)
out TCCR0B, r16
loop_new_byte:
eor r4, r4
dec r4
loop_check_tim_ovf:
sbis TIFR2, 0
rjmp loop_check_tim_ovf
/* Because timer 0 has no settable top value, we need to set the TCNT register to a desired value. */
out TCNT0, r18
/* Check the bit and set the */
out OCR0B, r20
sbrc r17,7
out OCR0B, r21
lsl r4
lsl r17
sbrc r4, 7
rjmp loop_check_tim_ovf
ld r17, x+
/* Clear the output to push a device reset */
OUT_CLR
DELAY_50_us
mov r4, r0
loop_send_bit:
next_byte_1:
LD r17, X
and r17, r4
tst r17
brne is_one
is_zero:
/* Is zero */
ldi Yh, HIGH((FCPU / (1 / 0.00000035)) / 4)
ldi Yl, LOW((FCPU / (1 / 0.00000035)) / 4)
OUT_SET
loop_0_1:
sbiw Y, 1
brne loop_0_1
OUT_CLR
ldi Yh, HIGH((FCPU / (1 / 0.0000008)) / 4)
ldi Yl, LOW((FCPU / (1 / 0.0000008)) / 4)
loop_0_0:
sbiw Y, 1
brne loop_0_0
rjmp check_if_byte_sent
is_one:
/* Is one */
ldi Yh, HIGH((FCPU / (1 / 0.0000007)) / 4)
ldi Yl, LOW((FCPU / (1 / 0.0000007)) / 4)
OUT_SET
loop_1_1:
sbiw Y, 1
brne loop_1_1
OUT_CLR
ldi Yh, HIGH((FCPU / (1 / 0.0000006)) / 4)
ldi Yl, LOW((FCPU / (1 / 0.0000006)) / 4)
loop_1_0:
sbiw Y, 1
brne loop_1_0
rjmp check_if_byte_sent
check_if_byte_sent:
lsr r4
tst r4
brne loop_send_bit
cp xl, r2
cpc xh, r3
brne loop_new_byte
/* Deactivate the timmer clock */
ldi r16, (0 << WGM02) | (0 << CS02) | (0 << CS01) | (0 << CS00)
out TCCR0B, r16
/* Disconnect OC0B pin */
ldi r16, (0 << COM0B1) | (0 << COM0B0) | (1 << WGM01) | (1 << WGM00)
out TCCR0A, r16
brne next_byte
OUT_SET
DELAY_50_us
OUT_CLR
ret
next_byte:
mov r4, r0
adiw x, 1
rjmp next_byte_1
......@@ -2,11 +2,11 @@
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......@@ -28,32 +28,54 @@
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......@@ -61,7 +83,12 @@
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......@@ -69,6 +96,15 @@
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