Commit b0ae7265 authored by MorgothCreator's avatar MorgothCreator

Some updates.

parent 6e742ee3
Pipeline #20 failed with stages
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="VERILOG_XMEGA_CORE_LATTICE" device="LCMXO3LF-6900C-5BG256C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
<Options def_top="uart_s" top="top_uc"/>
<Source name="top_uc.v" type="Verilog" type_short="Verilog">
<Options top_module="top_uc"/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/alu.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/mem.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/reg.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/xmega.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/xmega_v.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/io_s_h.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/pio_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/rtc_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/spi_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/twi_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/uart_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core1ROM.mem" type="Unknown Type" type_short="Unknown">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="VERILOG_XMEGA_CORE_LATTICE.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="VERILOG_XMEGA_CORE_LATTICE1.sty"/>
</BaliProject>
No preview for this file type
No preview for this file type
......@@ -5,25 +5,29 @@ Sections:
Idx Name Size VMA LMA File off Algn
0 .text 0000032e 00000000 00000000 00000074 2**1
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .bss 00000008 00800060 00800060 000003a2 2**0
1 .data 00000000 00800060 00800060 000003a2 2**0
CONTENTS, ALLOC, LOAD, DATA
2 .bss 00000008 00800060 00800060 000003a2 2**0
ALLOC
2 .comment 00000030 00000000 00000000 000003a2 2**0
3 .comment 00000030 00000000 00000000 000003a2 2**0
CONTENTS, READONLY
3 .debug_aranges 00000040 00000000 00000000 000003d2 2**0
4 .note.gnu.avr.deviceinfo 0000003c 00000000 00000000 000003d4 2**2
CONTENTS, READONLY
5 .debug_aranges 00000040 00000000 00000000 00000410 2**0
CONTENTS, READONLY, DEBUGGING
4 .debug_info 00000549 00000000 00000000 00000412 2**0
6 .debug_info 00000826 00000000 00000000 00000450 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_abbrev 000000f3 00000000 00000000 0000095b 2**0
7 .debug_abbrev 000003ac 00000000 00000000 00000c76 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_line 000000e9 00000000 00000000 00000a4e 2**0
8 .debug_line 00000388 00000000 00000000 00001022 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_frame 000000e0 00000000 00000000 00000b38 2**2
9 .debug_frame 000000e0 00000000 00000000 000013ac 2**2
CONTENTS, READONLY, DEBUGGING
8 .debug_str 0000016d 00000000 00000000 00000c18 2**0
10 .debug_str 0000027a 00000000 00000000 0000148c 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_loc 000002b3 00000000 00000000 00000d85 2**0
11 .debug_loc 000002b3 00000000 00000000 00001706 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_ranges 00000030 00000000 00000000 00001038 2**0
12 .debug_ranges 00000030 00000000 00000000 000019b9 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
......@@ -86,44 +90,44 @@ void delay(unsigned long time)
3c: a8 2f mov r26, r24
3e: 97 2f mov r25, r23
40: 86 2f mov r24, r22
42: 80 93 60 00 sts 0x0060, r24
46: 90 93 61 00 sts 0x0061, r25
4a: a0 93 62 00 sts 0x0062, r26
4e: b0 93 63 00 sts 0x0063, r27
52: 10 92 64 00 sts 0x0064, r1
56: 10 92 65 00 sts 0x0065, r1
5a: 10 92 66 00 sts 0x0066, r1
5e: 10 92 67 00 sts 0x0067, r1
42: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <__DATA_REGION_ORIGIN__>
46: 90 93 61 00 sts 0x0061, r25 ; 0x800061 <__DATA_REGION_ORIGIN__+0x1>
4a: a0 93 62 00 sts 0x0062, r26 ; 0x800062 <__DATA_REGION_ORIGIN__+0x2>
4e: b0 93 63 00 sts 0x0063, r27 ; 0x800063 <__DATA_REGION_ORIGIN__+0x3>
52: 10 92 64 00 sts 0x0064, r1 ; 0x800064 <__DATA_REGION_ORIGIN__+0x4>
56: 10 92 65 00 sts 0x0065, r1 ; 0x800065 <__DATA_REGION_ORIGIN__+0x5>
5a: 10 92 66 00 sts 0x0066, r1 ; 0x800066 <__DATA_REGION_ORIGIN__+0x6>
5e: 10 92 67 00 sts 0x0067, r1 ; 0x800067 <__DATA_REGION_ORIGIN__+0x7>
do
{
STimerCnt--;
62: 20 91 60 00 lds r18, 0x0060
66: 30 91 61 00 lds r19, 0x0061
6a: 40 91 62 00 lds r20, 0x0062
6e: 50 91 63 00 lds r21, 0x0063
72: 60 91 64 00 lds r22, 0x0064
76: 70 91 65 00 lds r23, 0x0065
7a: 80 91 66 00 lds r24, 0x0066
7e: 90 91 67 00 lds r25, 0x0067
62: 20 91 60 00 lds r18, 0x0060 ; 0x800060 <__DATA_REGION_ORIGIN__>
66: 30 91 61 00 lds r19, 0x0061 ; 0x800061 <__DATA_REGION_ORIGIN__+0x1>
6a: 40 91 62 00 lds r20, 0x0062 ; 0x800062 <__DATA_REGION_ORIGIN__+0x2>
6e: 50 91 63 00 lds r21, 0x0063 ; 0x800063 <__DATA_REGION_ORIGIN__+0x3>
72: 60 91 64 00 lds r22, 0x0064 ; 0x800064 <__DATA_REGION_ORIGIN__+0x4>
76: 70 91 65 00 lds r23, 0x0065 ; 0x800065 <__DATA_REGION_ORIGIN__+0x5>
7a: 80 91 66 00 lds r24, 0x0066 ; 0x800066 <__DATA_REGION_ORIGIN__+0x6>
7e: 90 91 67 00 lds r25, 0x0067 ; 0x800067 <__DATA_REGION_ORIGIN__+0x7>
82: af ef ldi r26, 0xFF ; 255
84: 3a d1 rcall .+628 ; 0x2fa <__adddi3_s8>
86: 20 93 60 00 sts 0x0060, r18
8a: 30 93 61 00 sts 0x0061, r19
8e: 40 93 62 00 sts 0x0062, r20
92: 50 93 63 00 sts 0x0063, r21
96: 60 93 64 00 sts 0x0064, r22
9a: 70 93 65 00 sts 0x0065, r23
9e: 80 93 66 00 sts 0x0066, r24
a2: 90 93 67 00 sts 0x0067, r25
86: 20 93 60 00 sts 0x0060, r18 ; 0x800060 <__DATA_REGION_ORIGIN__>
8a: 30 93 61 00 sts 0x0061, r19 ; 0x800061 <__DATA_REGION_ORIGIN__+0x1>
8e: 40 93 62 00 sts 0x0062, r20 ; 0x800062 <__DATA_REGION_ORIGIN__+0x2>
92: 50 93 63 00 sts 0x0063, r21 ; 0x800063 <__DATA_REGION_ORIGIN__+0x3>
96: 60 93 64 00 sts 0x0064, r22 ; 0x800064 <__DATA_REGION_ORIGIN__+0x4>
9a: 70 93 65 00 sts 0x0065, r23 ; 0x800065 <__DATA_REGION_ORIGIN__+0x5>
9e: 80 93 66 00 sts 0x0066, r24 ; 0x800066 <__DATA_REGION_ORIGIN__+0x6>
a2: 90 93 67 00 sts 0x0067, r25 ; 0x800067 <__DATA_REGION_ORIGIN__+0x7>
}while(STimerCnt);
a6: 20 91 60 00 lds r18, 0x0060
aa: 30 91 61 00 lds r19, 0x0061
ae: 40 91 62 00 lds r20, 0x0062
b2: 50 91 63 00 lds r21, 0x0063
b6: 60 91 64 00 lds r22, 0x0064
ba: 70 91 65 00 lds r23, 0x0065
be: 80 91 66 00 lds r24, 0x0066
c2: 90 91 67 00 lds r25, 0x0067
a6: 20 91 60 00 lds r18, 0x0060 ; 0x800060 <__DATA_REGION_ORIGIN__>
aa: 30 91 61 00 lds r19, 0x0061 ; 0x800061 <__DATA_REGION_ORIGIN__+0x1>
ae: 40 91 62 00 lds r20, 0x0062 ; 0x800062 <__DATA_REGION_ORIGIN__+0x2>
b2: 50 91 63 00 lds r21, 0x0063 ; 0x800063 <__DATA_REGION_ORIGIN__+0x3>
b6: 60 91 64 00 lds r22, 0x0064 ; 0x800064 <__DATA_REGION_ORIGIN__+0x4>
ba: 70 91 65 00 lds r23, 0x0065 ; 0x800065 <__DATA_REGION_ORIGIN__+0x5>
be: 80 91 66 00 lds r24, 0x0066 ; 0x800066 <__DATA_REGION_ORIGIN__+0x6>
c2: 90 91 67 00 lds r25, 0x0067 ; 0x800067 <__DATA_REGION_ORIGIN__+0x7>
c6: a0 e0 ldi r26, 0x00 ; 0
c8: 24 d1 rcall .+584 ; 0x312 <__cmpdi2_s8>
ca: 59 f6 brne .-106 ; 0x62 <__SREG__+0x23>
......@@ -511,10 +515,10 @@ void center_to_center(unsigned long times)
2d8: ae ce rjmp .-676 ; 0x36 <delay>
000002da <main>:
int
main()
{
while(1)
//asm("2fba");
while(1)
{
left_to_right(delay_cycles);
2da: 68 e6 ldi r22, 0x68 ; 104
......
This diff is collapsed.
......@@ -145,7 +145,7 @@ void center_to_center(unsigned long times)
int
main()
{
while(1)
while(1)
{
left_to_right(delay_cycles);
right_to_left(delay_cycles);
......
......@@ -6,37 +6,37 @@
<Source name="top_uc.v" type="Verilog" type_short="Verilog">
<Options top_module="top_uc"/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/alu.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/alu.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/mem.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/mem.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/reg.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/reg.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/xmega.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/xmega.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/xmega_v.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/xmega_v.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/IO/io_s_h.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/io_s_h.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/IO/pio_s.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/pio_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/IO/rtc_s.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/rtc_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/IO/spi_s.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/spi_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/IO/twi_s.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/twi_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/8BIT/ATXMEGA/IO/uart_s.v" type="Verilog" type_short="Verilog">
<Source name="../ip/CORE/8BIT/ATXMEGA/IO/uart_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core1ROM.mem" type="Unknown Type" type_short="Unknown">
......
#Start recording tcl command: 1/24/2020 17:58:26
#Project Location: C:/GitHub/rtl/xmega-tst-lattice; Project name: VERILOG_XMEGA_CORE_LATTICE
prj_project open "C:/GitHub/rtl/xmega-tst-lattice/VERILOG_XMEGA_CORE_LATTICE.ldf"
prj_src remove "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/alu.v" "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/mem.v" "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/reg.v" "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/xmega.v" "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/xmega_v.v" "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/IO/io_s_h.v" "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/IO/pio_s.v" "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/IO/rtc_s.v" "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/IO/spi_s.v" "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/IO/twi_s.v" "C:/GitHub/rtl/VERILOG-IP/CORE/8BIT/ATXMEGA/IO/uart_s.v"
prj_src add "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/alu.v" "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/mem.v" "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/reg.v" "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/xmega.v" "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/xmega_v.v"
prj_src add "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/IO/io_s_h.v" "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/IO/pio_s.v" "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/IO/rtc_s.v" "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/IO/spi_s.v" "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/IO/twi_s.v" "C:/GitHub/rtl/ip/CORE/8BIT/ATXMEGA/IO/uart_s.v"
prj_run Export -impl impl1
prj_src add "C:/GitHub/rtl/risc-v-tst-lattice/sram.ipx"
prj_src add "C:/GitHub/rtl/risc-v-tst-lattice/rom.ipx"
prj_src remove "C:/GitHub/rtl/risc-v-tst-lattice/sram.ipx" "C:/GitHub/rtl/risc-v-tst-lattice/rom.ipx"
prj_run Synthesis -impl impl1
prj_run Map -impl impl1
prj_run PAR -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
#Stop recording: 1/25/2020 15:26:04
......@@ -5,28 +5,28 @@
<Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1579882701"/>
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1579882704"/>
<Task name="Bitgen" build_result="0" update_result="2" update_time="1579882701"/>
<Task name="Jedecgen" build_result="0" update_result="2" update_time="1579882704"/>
<Task name="Jedec4Xo3l" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen4Xo3l" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Map" build_result="2" build_time="1579882649">
<Task name="Map" build_result="2" update_result="0" update_time="1579882649"/>
<Milestone name="Map" build_result="0" build_time="1579882649">
<Task name="Map" build_result="0" update_result="2" update_time="1579882649"/>
<Task name="MapTrace" build_result="0" update_result="3" update_time="0"/>
<Task name="MapVerilogSimFile" build_result="2" update_result="0" update_time="1579882652"/>
<Task name="MapVerilogSimFile" build_result="0" update_result="2" update_time="1579882652"/>
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="PAR" build_result="2" build_time="1579882694">
<Task name="PAR" build_result="2" update_result="0" update_time="1579882694"/>
<Task name="PARTrace" build_result="2" update_result="0" update_time="1579882695"/>
<Task name="IOTiming" build_result="2" update_result="0" update_time="1579882698"/>
<Milestone name="PAR" build_result="0" build_time="1579882694">
<Task name="PAR" build_result="0" update_result="2" update_time="1579882694"/>
<Task name="PARTrace" build_result="0" update_result="2" update_time="1579882695"/>
<Task name="IOTiming" build_result="0" update_result="2" update_time="1579882698"/>
</Milestone>
<Milestone name="Synthesis" build_result="2" build_time="1579882647">
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1579882647"/>
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1579882704"/>
<Milestone name="Synthesis" build_result="0" build_time="1579882647">
<Task name="Lattice_Synthesis" build_result="0" update_result="2" update_time="1579882647"/>
<Task name="LSE_Compile" build_result="0" update_result="2" update_time="1579882704"/>
</Milestone>
<Milestone name="TOOL_Report" build_result="0" build_time="0">
<Task name="HDLE" build_result="2" update_result="0" update_time="1579882633"/>
<Task name="HDLE" build_result="0" update_result="2" update_time="1579882633"/>
<Task name="BKM" build_result="0" update_result="2" update_time="0"/>
<Task name="SSO" build_result="0" update_result="2" update_time="0"/>
<Task name="PIODRC" build_result="0" update_result="2" update_time="0"/>
......
......@@ -62,7 +62,7 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2020/01/24 18:19:19</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2020/01/25 15:25:53</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
......
<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="C:/GitHub/VERILOG-XMEGA-CORE-LATTICE/promote.xml" version="Diamond (64-bit) 3.10.3.144" date="Sun Jan 06 20:06:23 2019" vendor="Lattice Semiconductor Corporation" >
<userSetting name="C:/GitHub/rtl/xmega-tst-lattice/promote.xml" version="Diamond (64-bit) 3.11.0.396.4" date="Sat Jan 25 15:26:04 2020" vendor="Lattice Semiconductor Corporation" >
<msg mid="35931002" type="Warning" />
<msg mid="35931038" type="Warning" />
<msg mid="35901209" type="Warning" />
......
......@@ -3,7 +3,7 @@
<ReportView version="2.0">
<Implement name="impl1">
<ToolReport id="tooldec" path="" status="0"/>
<ToolReport id="toolhle_genhierarchy" path="C:/GitHub/VERILOG-XMEGA-CORE-LATTICE/impl1/hdla_gen_hierarchy.html" status="1"/>
<ToolReport id="toolhle_genhierarchy" path="C:/GitHub/rtl/xmega-tst-lattice/impl1/hdla_gen_hierarchy.html" status="1"/>
<ToolReport id="toolpio" path="" status="0"/>
<ToolReport id="toolsso" path="" status="0"/>
</Implement>
......
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